Design of Low Power Arithmetic Unit Based on Reversible Logic

International Journal of VLSI and Signal

Processing Applications, Vol. 1, Issue 1(30- 38)

DESIGN OF LOW POWER ARITHMETIC UNIT BASED ON REVERSIBLE LOGIC

Ravish Aradhya H V1, Muralidhara K N2, Praveen Kumar B V3

1,3Department of Electronics and Communication Engineering, R V college of Engineering, Bangalore

2Department of Electronics and Communication Engineering, PES college of Engineering, Bangalore

1ravisharadhya@rvce.edu.in, 2knm08@rediffmail.com, 3 praveenbvk@gmail.com

Abstract

In VLSI designs today, the device dimensions are shrinking exponentially and the circuit complexity is also growing exponentially. Further, device scaling is limited by the power dissipation; demanding for better power optimizations methods. Reversible Logic is becoming more and more prominent special optimization technique having its applications in Low Power CMOS designs, Quantum Computing, Nanotechnology and Optical Computing. Reversibility plays an important role when energy efficient computations are to be designed. An ALU is a fundamental building block of a central processing unit (CPU) in any computing system. In this paper, as a part of ALU, a Reversible low power Arithmetic Unit based on a Parallel Binary Adder/Subtractor is proposed. In our design, the full Adders are realized using Peres gates which form one of the basic and efficient reversible gates. Peres gates offer the advantage of low quantum cost, low garbage output and importantly synthesizable. The performance analysis is verified using number reversible gates, Garbage outputs and Quantum Cost. Many adder/subtractor architectures have been proposed. By using suitable control logic to one of the input variables of parallel adder, various arithmetic operations can be achieved. In this paper data transfer, addition, subtraction, increment, decrement and many other Arithmetic operations are realized using reversible gates.

Key Words: Power Optimization, Quantum computing, Reversible Logic, Garbage output, Quantum Cost, Low Power, Reversible Parallel Binary Adder/Subtractor, Reversible Arithmetic Unit, Peres Gate, Fredkin Gate.

I. Introduction

The advancement in VLSI designs and particularly portable device technologies and increasingly high computation requirements, lead to the design of faster, smaller and more complex electronic Systems. Power consumption is an important issue in modern VLSI designs. The advent of multi-giga-hertz processors, high-end electronic gadgets bring with them an increase in system complexity, high density packages and a concern on power consumption. Power optimization can be done at various abstraction levels in CMOS VLSI design as indicated in Figure 1. That is at Device (Technology) level; Circuit level, Logic level, Architecture (System) level, Algorithmic level, etc. One such method at circuit logic level is energy recovery method, which employs reversible logic gates [23].

Figure 1. Power Optimization at various abstraction levels in CMOS design

According to R. Landauer's research [2], energy (heat) of KT ln 2 is dissipated for every

International Journal of VLSI and Signal

Processing Applications, Vol. 1, Issue 1(30- 38)

irreversible bit operation, where K is the Boltzmann's constant (1.3807×10-23 JK-1) and T is the operating temperature. For T equal to room temperature (300 K), KT ln2 is approximately 2.8×10 -21 J, which is small but non-negligible. In 1973, C. H. Bennett[1,3] concluded that no energy would dissipate from a system as long as the system was able to return to its initial state from its final state regardless of what occurred in between. It made clear that, for power not to be dissipated in the arbitrary circuit, it must be built from reversible gate. Reversible circuits are of particular interest in low power CMOS VLSI design.

II. Reversible Gates

The basic and simplest Reversible gate is conventional NOT gate and is a 1*1 gate. Controlled NOT (CNOT) gate is an example for a Reversible 2*2 gate. There are many 3*3 Reversible gates such as FG, TG, PG and Fredkin Gate. The Quantum Cost of 1*1 Reversible gates is zero and Quantum Cost of 2*2 Reversible gates is one. Any Reversible gate is realized by using 1*1 NOT gates and 2*2 Reversible gates, such as V, V+ (V is square root of NOT gate and V+ is its hermitian) and FG gate which is also known as CNOT gate. The V and V+ Quantum gates have the property given in the Equations 1, 2 and 3.

V * V = NOT (1)

V * V+ = V+ * V = I (2)

V+ * V+ = NOT (3)

The Quantum Cost of a Reversible gate is calculated by counting the number of V, V+ and CNOT gates.

A. NOT Gate

The basic Reversible 1*1 gate is CMOS NOT Gate with zero Quantum Cost is as shown in the Figure 2.

Figure 2. Reversible NOT gate

B. Feynman / CNOT Gate

The Reversible 2*2 gate with Quantum Cost of one having mapping input (A, B) to output (P = A, Q= AB) is as shown in the Figure 3.

Figure 3. Reversible Feynman/CNOT gate (FG)

C. Toffoli Gate

The Reversible 3*3 gate with three inputs and three outputs. The inputs (A, B, C) mapped to the outputs (P=A, Q=B, R=A.BC) is as shown in the Figure 4.

Figure 4. Reversible Toffoli gate (TG)

Toffoli gate is one of the most popular Reversible gates and has Quantum Cost of 5. It requires 2V, 1 V+ and 2 CNOT gates. Its Quantum implementation is as shown in Figure5.

Figure 5. Quantum implementation of Toffoli Gate

D. Peres Gate

The three inputs and three outputs i.e., 3*3 reversible gate having inputs (A, B, C) mapping to outputs (P = A, Q = AÅ B, R = (A.B) Å C). Since it requires 2 V+, 1 V and 1 CNOT gate, it has the Quantum cost of 4. The Peres gate and its

International Journal of VLSI and Signal

Processing Applications, Vol. 1, Issue 1(30- 38)

Quantum implementation are as shown in the Figure 6 and 7 respectively.

Figure