Energy Efficiency: Power Management

Energy Efficiency: Power Management

Abstract:

Energy efficiency of computer systems is an important concern in variety of contexts. An energy efficient platform not only improves the operating cost but it also affect the scalability, reliability and performance of the systems. Achieving energy efficient platforms demands for green power management at complete system levels.

Maximizing energy saving techniques has become a challenge in the designing of computer system. Efficient power management needs to be implemented at each level of system. This paper describes different power management techniques that are used at different system level (architectural level operating system level and hardware & software level). Besides, techniques and advancement in the power management policies this paper also highlights the different approaches used at different level of power management.

Introduction:

Improvements in hardware structure made it possible to embed number of small electronic devices on a small chip. Software advancement made possible to measure the capabilities of a single chip. Computer technology evolution is offering the promise of more reliable and more useful devices and policies. Among other desired achievements, power management is also in the vision. Effective power management, at architecture level and at every stage of components and device, greatly contribute in the scalability of computer system.

To achieve better energy efficiency, numerous innovations and improvements have been made to system architecture as well as operating system [7, 9, 10, 14]. Instead of these innovation and improvements efficient power management is becoming more challenging task. Efficient power management needs better understanding of each level of system. To gain enough information and knowledge of power management this paper presents the over all view of power management that are used to achieve Green Solution.

This paper discussed different ideas and techniques proposed in the literature with the goal of developing power-aware computer systems. Various power management methods and techniques at design time and run time are described. Design time techniques are mainly based on simulation, sometimes assisted by measurements. Run time techniques, Dynamic Power Management (DPM) are applied at operating system level. They monitor the system workload to predict the future computational requirements and try to dynamically adapt the system behavior. Additionally, this paper also described few techniques applied in parallel systems.

This paper is organized as follow: Section-2 describes different power management levels with details about architectural level management. Section-3 defines power management levels techniques at operating system level that is Data Power Management, DPM. Section-4 presents hardware & software level data power management and techniques used for power management at hardware & software level. Section-5 explains power management in parallel or distributed systems.

2. Power Management Level

Today, in designing of processor and computers energy efficient components have gain enough importance [17]. The first need to use the energy efficiency concept is to know and understand the different sources of the energy at different level. At each level, power management has various dimensions. Power management levels are categorized as follow:

(2.1) Architectural Level Power Management (3) Operating System Level Power Management

(4) Hardware & Software (Process) level Power Management

(5) Power Management in Parallel Systems

2.1) Architectural Level Power Management:

Architectural level power management deals with the power management techniques implemented at design time. One of the architectural level power management that is becoming critical is CPU level Power Management. Power consumption at CPU level is becoming main target of the analysis [15]. CPU analysis are based on two level:

i) Cycle Level (ii) Instruction Level

i) Cycle Level: At cycle level, the task is to identify the active or busy units during each execution cycle [15, 16, 18]. At cycle level the need is, according to power consumption point of view, to know the capacity of the circuits, cache size, and number of register. Capacity of circuits tells the available bandwidth for the flow of different signals. As data are in shape of signals, these signals are related to the cache size. After storing of data cache has to access the data. If data is accessing for the first time registers are used to hold the data temporary. If operation is finished and registers are not released the signals will still traverse in the circuits and will result in waste of resources other than energy. For circuits capacitance Wattch [15] measure the internal capacity of the circuits preventing the overflow and dead lock situation.

Power timer [18] presented energy model that are used to measure the detail power of the different areas of the system. For cache and number of registers usage power timer use its analytical energy concept.

Besides, above-mentioned additions to the architecture an other critical aspect is the size of the register file. The use of larger register files and faster clock have increased the performance level but in contrast, it also limited the access of the register file in one cycle[19]. As a result, more energy is using in accessing these files. Same problem is been treated by [19] by splitting RFC (Register File Cache) into two sections. RFC caches a small set of registers in a faster and smaller structure. The splitting of the register file has contributed to the energy efficiency with the loss of .3% in performance [19]. The two parts after splitting are a FIFO cache, named SRFC (short term RFC) that are accessed in few cycles and other part is LRFC (long term RFC). LRFC can hold total 16 entries using a LRU replacement strategy. The change of this structure results in that 35% values will not be written to the register file because they are stored before the usage of register file.

ii) Instruction Level: Cycle level power efficiency techniques compute the energy efficiency at each cycle [16]. On other hand instruction level analysis allows to compute the total energy consumption of a program [18, 20]. For a separate instruction base cost [17], Instruction to instruction energy, can be measured but this